Currently, a network processor is generally used to forward a network packet in a packet forwarding processing device such as a router or a switch. The network processor refers to a programmable processor dedicated to processing a network packet, and many private circuits are integrated inside the network processor to increase a speed at which a network packet is processed.
According to differences between implementation manners in which the network processor processes a packet, the network processor may be roughly classified into two types. A first type of network processor is generally referred to as a run-to-complete architecture. The first type of network processor is characterized in that after receiving a network packet, the network processor allocates the network packet to an idle processor core for forwarding processing, and sends a processed network packet. In other words, processing of an entire network packet is completed on one processor core, and packet data does not move during the processing process. A second type of network processor is generally referred to as a pipelining architecture. This type of network processor is characterized in that after a network packet is received, the network packet is sent to a packet processing pipeline for forwarding processing, where the entire packet processing pipeline generally includes processing circuits at multiple levels, and a processing circuit at each level may complete one or more basic processing actions by programming. During the processing process, intermediate data is passed forward along the pipeline stage by stage. A Protocol Oblivious Forwarding mechanism may be considered as a series of match-action combinations, and may be easily implemented on a network processor of the pipelining architecture.
As a requirement on processing capabilities of a packet forwarding processing device continuously increase, a network packet processing rate provided by one packet processing pipeline has been gradually incapable of meeting the requirement. In this case, multiple pipelines are simply used in the prior art to process a network packet in parallel, which forms a parallel pipelining architecture, to provide a higher packet processing rate.
During a process of studying and practicing the prior art, the inventor finds that: a major problem of a parallel pipelining architecture used in the prior art is that a quantity of resources (for example, table lookup bandwidth, instruction bandwidth, power consumption) consumed by the parallel pipelining architecture increases proportionally to a quantity of parallel pipelines. However, a semiconductor technique develops far more slowly than a bandwidth requirement of a network device; therefore, it is a great challenge to implement a chip that provides these resources.